1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) having a cascade-connected type memory cell array capable of storing plural-bit information in the unit of bit.
2. Description of the Related Art
A DRAM cell which is now practically used has one MOS transistor used as a transfer gate and connected to a word line and a bit line and one capacitor connected to the transistor for information storage.
By taking into consideration the fact that it is required to enhance the integration density of the DRAM cells and reduce the cost for one bit, the inventor of this application proposed a cascade-connected type memory cell having such a construction as shown in FIGS. 1A, 2A, for example, and storing plural-bit information in the unit of bit and time-sequentially reading out the same (U.S. application Ser. No. 07/687,687) (JAPANESE PATENT APPLICATION No. H.2-104576).
In FIG. 1A, the memory cell includes three or more (in this example, five) MOS transistors Q1 to Q5 cascade-connected between a first node N1 and a second node N2, and a plurality of capacitors C1 to C4 for information storage which are connected at one end to the respective connection nodes between the cascade-connected MOS transistors.
The gates of the MOS transistors Q1 to Q5 are connected to respective word lines WL1 to WL5 of the memory cell array and the other ends of the capacitors C1 to C4 are commonly connected to a capacitor wiring 11 of the memory cell array (in this example, the capacitor wiring 11 is set to a plate potential VPL).
Further, the first node N1 and the second node N2 are commonly connected to a bit line BL of the memory cell array.
In the drawing, PR denotes a bit line precharge circuit connected to the bit line BL, 12 denotes a sense amplifier for sensing and amplifying the potential of the bit line BL, and 13 denotes a write circuit for setting the potential of the bit line BL according to write data.
Next, one example of the readout operation and the write operation of the DRAM cell of FIG. 1A is explained with reference to the timing waveform diagram of FIG. 1B.
The ON/OFF states of the word lines WL1 to WL5 are controlled at the timings shown in FIG. 1B to render the transistors Q1 to Q5 conductive in this order and then render the transistors Q1 to Q5 non-conductive in this order.
That is, when the word line WL1 is set into the ON state at the time t1 after the bit line BL is precharged to a preset potential by the bit line precharge circuit PR, the transistor Q1 is turned on to permit storage information of the capacitor C1 to be read out to the bit line BL via the transistor Q1 and sensed and amplified by the sense amplifier 12.
Next, when the word line WL2 is set into the ON state at the time t2 after the bit line BL is precharged again for a preset period of time, the transistor Q2 is turned on to permit storage information of the capacitor C2 to be read out to the bit line BL via the transistors Q2 and Q1.
Then, when the word line WL3 is set into the ON state at the time t3 after the bit line BL is precharged again, the transistor Q3 is turned on to permit storage information of the capacitor C3 to be read out to the bit line BL via the transistors Q3 to Q1.
Next, when the word line WL4 is set into the ON state at the time t4 after the bit line BL is precharged again, the transistor Q4 is turned on to permit storage information of the capacitor C4 to be read out to the bit line BL via the transistors Q4 to Q1.
After this, the word line WL1 is set into the OFF state to turn off the transistor Q1 and the word line WL5 is set into the ON state to turn on the transistor Q5 (the order of the operations may be reversed).
Next, when the word line WL2 is set into the OFF state at the time t5, the transistor Q2 is turned off to permit information (write data set by the write circuit 13) of the second node N2 to be written into the capacitor C1.
Next, when the word line WL3 is set into the OFF state at the time t6, the transistor Q3 is turned off to permit information of the node N2 to be written into the capacitor C2.
Next, when the word line WL4 is set into the OFF state at the time t7, the transistor Q4 is turned off to permit information of the node N2 to be written into the capacitor C3.
Next, when the word line WL5 is set into the OFF state at the time t8, the transistor Q5 is turned off to permit information of the node N2 to be written into the capacitor C4.
As is understood from the above explanation for the operation, according to the cascade-connected type cell of FIG. 1A, capacitor storage information can be read out to the first mode N1 in an order from the capacitor C1 which lies in the position near the first node N1 to the capacitor C4 which lies in the position farther from the node N1 by controlling the ON/OFF states of the transistors Q1 to Q5 in a preset order.
Further, information of the second node N2 can be written in an order from the capacitor C1 which lies in the position near the first node N1 to the capacitor C4 which lies in the position farther from the node N1 by controlling the ON/OFF states of the transistors Q1 to Q5 in a preset order.
A memory cell shown in FIG. 2A is connected at one end to a first node N1 for read/write and includes a cascade gate constructed by a plurality of (for example, four) first MOS transistors Q1 to Q4 cascade-connected and a plurality of information storing capacitors C1 to C4 which are each connected at one end to one of two ends of a corresponding one of the MOS transistors Q1 to Q4 which lies farther from the node N1.
The gates of the MOS transistors Q1 to Q4 are respectively connected to word lines WL1 to WL4 of the memory cell array and the node N1 is connected to a bit line BL of the memory cell array. PR denotes a bit line precharge circuit, 12 denotes a sense amplifier and 13 denotes a write circuit.
Next, one example of the readout operation and the write operation of the cascade-connected type DRAM cell of FIG. 2A is explained with reference to the timing waveform diagram of FIG. 2B.
The ON/OFF states of the word lines WL1 to WL4 are controlled at the timings shown in FIG. 2B to render the transistors Q1 to Q4 conductive in this order and then render the transistors Q4 to Q1 non-conductive in this order.
That is, when the word line WL1 is set into the ON state at the time t1 after the bit line BL is precharged to a preset potential by the bit line precharge circuit PR, the transistor Q1 is turned on to permit storage information of the capacitor C1 to be read out to the bit line BL via the transistor Q1 and sensed and amplified by the sense amplifier 12.
Next, when the word line WL2 is set into the ON state at the time t2 after the bit line BL is precharged again for a preset period of time, the transistor Q2 is turned on to permit storage information of the capacitor C2 to be read out to the bit line BL via the transistors Q2 and Q1.
Then, when the word line WL3 is set into the ON state at the time t3 after the bit line BL is precharged again, the transistor Q3 is turned on to permit storage information of the capacitor C3 to be read out to the bit line BL via the transistors Q3 to Q1.
Next, when the wordline WL4 is set into the ON state at the time t4 after the bit line BL is precharged again, the transistor Q4 is turned on to permit storage information of the capacitor C4 to be read out to the bit line BL via the transistors Q4 to Q1.
After this, when the word line WL4 is set into the OFF state at the time t5 to turn off the transistor Q4, information (write data set by the write circuit 13) of the bit line BL is written into the capacitor C4.
Next, when the word line WL3 is set into the OFF state at the time t6, the transistor Q3 is turned off to permit information of the bit line BL to be written into the capacitor C3.
Next, when the word line WL2 is set into the OFF state at the time t7, the transistor Q2 is turned off to permit information of the bit line BL to be written into the capacitor C2.
Next, when the word line WL1 is set into the OFF state at the time t8, the transistor Q1 is turned off to permit information of the bit line BL to be written into the capacitor C1.
As is understood from the above explanation for the operation, according to the cascade-connected type cell of FIG. 2A, capacitor storage information can be read out to the first node N1 in an order from the capacitor C1 which lies in the position near the first node N1 to the capacitor C4 which lies in the position farther from the node N1 by controlling the ON/OFF states of the transistors Q1 to Q4 in a preset order.
Further, information of the first node N1 can be written into the capacitors in an order from the capacitor C4 which lies in the position farther from the first node N1 to the capacitor C1 which lies in the position near the node N1 by controlling the ON/OFF states of the transistors Q1 to Q4 in a preset order.
Further, the cascade-connected type cells shown in FIGS. 1A, 2A can be formed with a higher integration density than a conventional DRAM using one-transistor/one-capacitor cells by use of the existing manufacturing process or without using a fine patterning technique in a modified manufacturing process, and therefore, the cost for one bit can be significantly reduced.
In addition, the inventor of this application proposed a semiconductor memory device having storing means for temporarily storing information time sequentially read out from the above-described cascade-connected type cell (U.S. application Ser. No. 07/721,255) (Japanese Patent Application No. H.3-41316).
In the above semiconductor memory device, data can be rewritten after the readout from a desired one of the capacitors of one cascade-connected type cell is effected and then the readout from another capacitor of the same cell is sequentially effected.
Further, the inventor of this application proposed a semiconductor memory device of a type for serially (sequentially) accessing a memory cell group in the same column of a cascade-connected type cell array while keeping the serial accessibility of the above-described cascade-connected type cell (U.S. application Ser. No. 07/850,318) (Japanese Patent Application No. H.3-74830).
The semiconductor memory device has a cascade-connected type cell array, utilizes a method for serially accessing a plurality of cells in the same column, and includes access means for time-serially reading out plural-bit information from a cell which stores storage information at the time of readout/rewrite for the cascade-connected type cell and sequentially rewriting the plural-bit information into a cell which is a different one of the cells in the same column and set in a non-use state. That is, the cells are serially accessed in the unit of column by using a method for using one extra cell for each column, reading data from a cell, and then storing (rewriting) the data into another cell which is accessed before reading out the data from the former cell and now set in a vacant state.
In the above serially accessible semiconductor memory cell, means For temporarily storing information time sequentially read out from the cells for rewriting at the time of readout/rewrite for the cell can be omitted and the high integration density can be attained. Therefore, the operation speed of an external memory device can be enhanced by replacing the above serially accessible semiconductor memory device by a memory device (such as a magnetic disk used as an external memory device of a computer system) for serially reading/writing data in the unit of block.
In the application field of the recent DRAMs, since the field of processing such as the block transfer with respect to the cache memory, processing or holding of image data which can be coped with by serial access is rapidly expanding, the application field of the above serially accessible semiconductor memory device is wide.
In order to further enhance the integration density and increase the capacity by suppressing the occupied area of the sense amplifier on the chip, one sense amplifier can be commonly used for a plurality of columns in a time sharing manner by selectively connecting the sense amplifier by use of a switching means. The technique for commonly using one sense amplifier for a plurality of columns in a time sharing manner in a DRAM cell array of a type for time-serially reading out plural-bit information is disclosed in "1991 IEEE ISSCC DIGEST OF TECHNICAL PAPERS pp. 107 `A Block-Oriented RAM with Half-Sized DRAM Cell and Quasi-Folded Data-Line Architecture` K. Kimura et al.
However, in a case where a shared sense amplifier system in which one sense amplifier is commonly used by four columns, for example, in a time sharing manner as described above is used as a DRAM having a cell array of a type for time-serially reading out plural-bit information, a readout signal from the cascade-connected type cell is simultaneously supplied to the four columns, and while data is being read out from one of the columns, the other three columns are set into a readout stand-by state.
If the potential of the bit line of one column for which the readout operation is now effected is changed to the full amplitude of the power source potential to effect the rewrite operation, the noise caused by the capacitive coupling between the bit lines occurs on the bit line (to which a readout signal from the memory cell is already supplied) of another column adjacent to the above column, and therefore, the amount of signal subsequently read out from the other column is significantly reduced so that the sense operation may be delayed and the sense operation may be sometimes erroneously effected to output erroneous data.